Select the files shift_register.vho and shift_register_tb.vhd and click Compile. b) Compile the files:Ĭircuit Design and Simulation with VHDL, 2nd Edition, V. A. Pedroni, MIT Press 5 ‐ Copy these two files to the ModelSim work directory and return to the ModelSim software. ‐ Compile the design. In the work directory, a simulation/modelsim (default name) subdirectory is automatically created, containing the files shift_register.vho and shift_register_vhd.sdo. ‐ Select Assignments > Settings > EDA Tools Settings > Simulation > Tool name > ModelSim‐Altera and click OK. Finally, inspect the resultsĤ. Performing Timing Simulation a) Go to Quartus to get the two additional files: ‐ Launch Quartus II and load the shift_register.vhd file. i) Clean the waveforms window by clicking the restart icon (compare to figure 1b). h) Repeat step (g) a few times. Note that the plot grows 720 ns each time. or selecting Simulate > Run > Run 100. Click then the zoom full icon g) Finally, run the simulation by clicking see the complete waveforms of figure 6d. f) Set the simulation time interval by selecting Simulate > Runtime Options and entering Default Run = 720 ns. e) Any signal in the wave list can be dragged up or down (reset and clock are usually wanted at the top). To do so, press and hold the left mouse button on the signal’s name and move it to the desired position. d) Click the right mouse button on shift_register_tb in figure 6c (top left corner) and select Add to > Wave > All items in region. This places the signal names (no waveforms yet) as shown in the center of figure 6c. This leads to figure 6c (without the waveforms yet). c) Expand the work library in figure 6b, select shift_register_tb, then click OK. (If you are debugging a file, you can compile it separately.)Ĭircuit Design and Simulation with VHDL, 2nd Edition, V. A. Pedroni, MIT Press 4ī) Select Simulate > Start Simulation. This leads to figure 6b. Select both files (shift_register.vhd and shift_register_tb.vhd) and click Compile. e) Select File > Change Directory and change to the directory created in step (a).ģ. Performing Functional Simulation For functional simulation, proceed below. For timing simulation, go to section 4.Ī) Select Compile > Compile or click. LIBRARY ieee USE ieee.std_logic_1164.all -ENTITY shift_register IS PORT (clk, rst, din: IN STD_LOGIC dout: OUT STD_LOGIC) END ENTITY -ARCHITECTURE mydesign OF shift_register IS BEGIN PROCESS (clk, rst) VARIABLE q: STD_LOGIC_VECTOR(0 TO 3) BEGIN IF rst='1' THEN q := (OTHERS => '0') ELSIF rising_edge(clk) THEN q := din & q(0 TO 2) END IF dout VHDL, which opens the VHDL editor. Type each file and save it in the directory created in step (a). Leave these files open, as shown in figure 5. ‐ An SDF (standard delay format) file (shift_register.sdo), which contains the propagation delays.Ĭircuit Design and Simulation with VHDL, 2nd Edition, V. A. Pedroni, MIT Press 2 To perform timing simulation, two additional files are needed, both generated by the synthesizer (Quartus II, for example): ‐ A post synthesis file (shift_register.vho). This tutorial is based on ModelSim 10.1d Altera Starter Edition (free at which accompanies, for example, Quartus II 13.0 sp1. The circuit used in this tutorial is the 4‐stage shift register of figure 1a. The waveforms to be generated for rst, clk, and din are shown in figure 1b, from which the waveforms shown for q and dout are expected.ġ. Files Needed for Simulation To perform functional simulation, two files must be created by the user (see figure 2): ‐ A design file (shift_register.vhd). This file contains all the commands and library inclusions the simulation requires.Circuit Design and Simulation with VHDL 2nd edition Volnei A. Pedroni MIT Press, 2010 Book web: Appendix D In the ModelSim* - Intel ® FPGA Edition software, open the PLL_RAM_run_msim_rtl_verilog.do file.
#How to use modelsim software
The Intel ® Quartus ® Prime software generates the PLL_RAM_run_msim_rtl_verilog_do file that defines the compilation and simulation instructions for the ModelSim* - Intel ® FPGA Edition simulator in the /simulation/modelsim/ directory in your project.
Enable Generate third-party EDA tool command scripts without running the EDA tool, and then click OK.Click Assignments > Settings > EDA Tool Settings > Simulation > More NativeLink Settings.The project opens in the Intel ® Quartus ® Prime GUI. To open the example design project, click File > Open Project, select the pll_ram.qpf project file, and then click OK.do file that runs the ModelSim* - Intel ® FPGA Edition simulator from the command line.
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